High speed serial multimedia interfaces including, for example, a high-definition multimedia interface (HDMI™) and a DisplayPort™, are interfaces that are used for transmitting uncompressed digital streams. Such interfaces connect digital multimedia source devices (e.g., a set-top box, a DVD player, a computer, a video game console, etc.) to a compatible multimedia sink device, e.g., a high definition television. Other multimedia interface standards that define the digital display interfaces of digital audio/video interconnections for handled devices have been recently defined. Examples for such multimedia interface standards include the mobile high-definition link (MHL) and Mobility DisplayPort™ (or MyDP).
Generally, the multimedia interface standards have been designed to transfer high-definition multimedia (video/audio) and control signals from a source device to a sink device over a physical medium cable. The signals are transferred at a high baud which is synchronized by a high frequency clock signal.
For example, in a HDMI system, a multimedia source device is connected to a multimedia sink device through a HDMI cable. A multimedia source transmits high speed data using transmission minimized differential signaling (TMDS®) characters. The TMDS characters encapsulate video, audio, and auxiliary data, and are carried over three TMDS channels. A multimedia sink device receives the TMDS characters and converts them into digital video streams and control codes that are encoded in the auxiliary data. The control codes include ESS, HSYNC and VSYNC signals. In addition, configuration, system-level control, management, and status information is exchanged between the multimedia source sink devices. The system-level control signals, such as display data channel (DDC) and consumer electronics control (CEO), are also exchanged between the source and sink devices.
A clock, typically running at a video pixel rate, is transmitted from the source device on a clock channel and is used by the sink device as a frequency reference for data recovery of TMDS characters. The TMDS characters are transferred, over the TMDS channels, at a rate synchronized with the video pixel rate transported over the clock channel. A frequency (i.e., a video pixel rate) of the clock signal determines the number of pixels transmitted per second and is determined by the HDMI standard. For example, the frequency of a clock signal is from 250 Mb/Sec up to 3.4 Gb/Sec.
A distributed peripheral interconnect bus connects a root component to endpoint components that are located remotely from each other. For example, such a bus allows the connectivity, between root and endpoint components over a wireless medium or a wireless channel.
An exemplary diagram of a distributed interconnect bus apparatus 100 is shown in FIG. 1. The apparatus 100 comprises an upstream bridge 110 connected to a root component 120 and a downstream bridge 130 connected to an endpoint component 140. The root component 120 is typically a host bridge of a computing device while the endpoint component 140 provides a connectivity to a peripheral device, such as a monitor.
The bridges 110 and 130 communicate over a link 170 which is the medium used to transfer the data between the components 120 and 140. The medium may be, but is not limited to, air, a copper cable, a fiber optic, and so on. That is, the interconnect bus apparatus 100 forms a distributed bus for transferring data between remote devices coupled to the root component 120 and the endpoint component 140. The transport protocol used to carry data between the components 120 and 140 may be, but is not limited to, IEEE 802.11ad (WiGig), IEEE 802.11x (Wi-Fi), Ethernet, Infiniband, and the like. Each of the bridges 110 and 130 includes or is connected to a physical (PHY) layer module (154, 162) and a MAC layer module (152, 164) compliant with the transport protocol.
The apparatus 100 also enables distributed connectivity of high speed serial multimedia interfaces, such as those mentioned above. In such a configuration, the root component 120 is connected to a multimedia source device and the endpoint component 140 is connected a multimedia sink device. Therefore, to enable proper connectivity over the distributed medium, e.g., a wireless channel, the multimedia signals streamed to the multimedia sink device should be synchronized with the clock signal of the respective multimedia interface (hereinafter a “multimedia interface clock signal”). For example, the TMDS characters should be transferred together with a multimedia interface clock signal, to enable a distributed HDMI connectivity.
As noted above, the multimedia interface clock signal generated by the multimedia source is used by the multimedia sink to recover the data. In the arrangement shown in FIG. 1, the multimedia interface clock signal is not transferred over a wire connecting the root and endpoint components 120 and 140. Thus, there is a need to transfer and synchronize the multimedia interface clock signal between the upstream and downstream bridges 110 and 130. It should be noted that the multimedia interface clock signal has a frequency that is different than the frequency of the radio signals utilized for the wireless transmission.
Current attempts to synchronize the transfer of a multimedia interface clock signal over a distributed medium include sending timestamp messages from a wireless transmitter 150 to a wireless receiver 160. The timestamp messages can be then used by a phase-locked loop (PLL) circuitry, in the downstream bridge 130, to lock on the multimedia interface clock signal generated by the multimedia source (root component 120). The timestamp is measured and the timestamp message is derived by the downstream bridge 110. However, such a solution would be feasible only if the jitter of the timestamp messages is very low, e.g., less than 10 microseconds. This requirement cannot be met when, for example, retransmitting packets that include the original timestamp messages.
A conventional process for synchronizing the multimedia interface clock signal using timestamps is further described with a reference to FIG. 2. A source clock (201) generated by a source device is input into a timestamp (TS) measurement unit 210 that records the clock cycles that passed since the last generated timestamp. The unit 210 outputs a timestamp message indicating the counted clock cycles. The timestamp messages are later encapsulated in data packets together with multimedia and control signals (e.g., TMDS characters) by a packetizer 220. This process is typically performed by a wireless transmitter.
The packets are transmitted over a wireless medium to a wireless receiver where the data packets are de-packetized by a de-packetizer 230 and the timestamp message is extracted by a timestamp (TS) extraction unit 240. Then, the timestamp value is transferred to the PLL circuit 250 that generates a clock signal (202) for the sink device having a frequency in proximity to a frequency of a clock signal generated by the multimedia source device.
Typically, a PLL circuit generates an output signal having a phase that is related to the phase of an input “reference” signal, i.e., the source clock as represented by the timestamp messages. Frequency is the derivative of the phase, thus when the source and sink clock signals' phases are in a lock state, their frequencies are also locked, i.e., synchronized. However, as mentioned above, this solution is not tolerant to jitter, thus it is inefficient for distributed connectivity and particularly a wireless medium.
Therefore, it would be advantageous to provide a high performance interconnect bus that would allow a distributed multimedia interface connectivity. It would be further advantageous if a solution was presented for synchronizing clocks of wired connections when transmitted over a wireless channel.